New ternary inverter with memory function using silicon feedback field-effect transistors

In this study, we present a fully complementary metal–oxide–semiconductor-compatible ternary inverter with a memory function using silicon feedback field-effect transistors (FBFETs). FBFETs operate with a positive feedback loop by carrier accumulation in their channels, which allows to achieve excellent memory characteristics with extremely low subthreshold swings. This hybrid operation of the switching and memory functions enables FBFETs to implement memory operation in a conventional CMOS logic scheme. The inverter comprising p- and n-channel FBFETs in series can be in ternary logic states and retain these states during the hold operation owing to the switching and memory functions of FBFETs. It exhibits a high voltage gain of approximately 73 V/V, logic holding time of 150 s, and reliable endurance of approximately 105. This ternary inverter with memory function demonstrates possibilities for a new computing paradigm in multivalued logic applications.

drive-in was performed at 1100 °C for 30 min. A silicon dioxide (SiO 2 ) gate dielectric with a thickness of 22 nm was thermally grown at 850 °C, and a polysilicon gate was formed on top of a channel using a low-temperature chemical vapor deposition (LPCVD) and photolithography. Tetraethyl orthosilicate gate sidewall spacers with a length of approximately 200 nm were formed using LPCVD. BF 2 + ions at a dose of 6 × 10 13 cm −2 at 40 keV and P + ions with a dose of 1 × 10 14 cm −2 at 60 keV were implanted to form p-type nongated (for p-FBFET) and n-type nongated region (for n-FBFET) regions, respectively. In addition, the p + drain contact regions were heavily doped with BF 2 + ions at a dose of 3 × 10 15 cm −2 at 30 keV. The n + source contact regions were heavily doped with P + ions at a dose of 3 × 10 15 cm −2 at 100 keV for the p-FBFET and at a dose of 4 × 10 15 cm −2 at 50 keV for n-FBFET. Subsequently, the wafer was annealed at 1000 °C for 30 min and then at 1050 °C for 30 s using a rapid thermal annealing system to activate the implanted dopants. Finally, the drain, source, and gate electrodes were made of Ti/TiN/Al/TiN metal alloy using sputtering and photolithography.
Measurements. The electrical properties were measured at room temperature using an Agilent HP4155C semiconductor parameter analyzer, a Tektronix AFG 31000 arbitrary function generator, and a Tektronix MDO3054 mixed-domain oscilloscope. The cross-section image of the FBFET was obtained using transmission electron microscopy (TEM; Tecnai G2 F20, FEI).

Results and discussion
A three-dimensional schematic and optical image of a ternary inverter comprising single-gated n-and p-FBFETs connected in series are shown in Fig. 1a,b, respectively. The basic structure of FBFETs consists of a heavily doped p + drain region, heavily doped n + source region, and p-n channel region. Although the p-n-p-n energy band structure of the FBFET is similar to those of tunneling devices, the band-to-band tunneling (BTBT) is not a significant factor in the FBFET operation. In the FBFET, the forward bias is used to generate the positive feedback mechanism, whereas tunneling devices use reverse bias to operate with BTBT mechanism. As a result, our device www.nature.com/scientificreports/ does not suffer from degradation in switching speed caused by the BTBT. The channel lengths of the n-and p-FBFET were 5 and 4 µm, respectively, and different channel lengths were used to achieve identical channel resistances for these FBFETs in the on state. The source of the n-FBFET is connected to V SS , and the drain of the p-FBFET is connected to V DD as the power supply voltage. The gates of the n-and p-FBFET were shared as an input node, and the drain of the n-FBFET and source of the p-FBFET were shared as an output node.   On the other hand, the decrease in the output voltage can be explained in terms of charging in the FBFET and the output impedance limitation of our oscilloscope. Due to charging in the FBFET, the FBFET acts as a capacitor and causes the output voltage drop. The maximum output impedance of our oscilloscope is 1 MΩ that is close to the on-state channel resistance of the FBFETs. Accordingly, the output voltage was divided between the FBFET channel resistance and the oscilloscope impedance. Figure 4 shows the voltage hysteresis characteristics (VHC) of the ternary inverter. The hysteresis curves are divided into four regions: I, II, III, and IV. In these regions, the on/off states of the n-and p-FBFET and the logic '0'/'− 1' states of the ternary inverter are examined using the representative transfer characteristics shown in  22 . Accordingly, the positive feedback loop is eliminated, and the n-FBFET is in the off state owing to the emission of accumulated holes. Thus, the output of the ternary inverter reveres from the logic '0' state to the logic '1' state. After the write operation, the holding process was performed by sensing the difference in the V OUT of logic '1' and '0' states at V IN = − 2.0 V, which is within the range of MW1. During the hold operation, the ternary inverter stably maintains in the logic '1' and '0' states. Moreover, the memory operation of logic states '0' and '− 1' using MW2 (region III) is depicted in Fig. 5b. When a V IN of − 1.5 V (− 0.3 V) is applied, the ternary inverter reverses the logic states from '− 1' ('0') to '0' ('− 1'). For the holding operation of logic '0' and '− 1' states, V IN is set to − 0.9 V, which is within the range of MW2. During the hold operation, FBFETs maintained their on or off states; thus, the ternary inverter memorizes the logic '0' or '− 1' states. In our ternary inverter, the memory characteristics allow to maintain the ternary output voltage without any additional circuit. Accordingly, the ternary inverter can be embedded in the CPU and it can replace the volatile memory block or D-latch circuit.
The retention properties of the proposed ternary inverter using each of the separate MWs (MW1 and MW2) are shown in Fig. 6a,b. After write pulses with a time width of 2 s are applied, the ternary inverter stably maintains the logic '1' or '0' states at V IN = − 2.0 V and the logic '0' or '− 1' states at V IN = − 0.9 V for a holding time of 150 s. Figure 6c,d show the endurance characteristics of the ternary inverter as a function of the number of write/hold memory cycles. During the endurance evaluation, the pulse cycles of the memory operations using MW1 (Fig. 6c) and MW2 (Fig. 6d) are the same as those in Fig. 5a,b, respectively. The presented ternary inverter  www.nature.com/scientificreports/ showed reliable characteristics even after 10 5 cycles of memory operations, implying that the degradation of the three logic states of the ternary inverter is negligible during memory operations.

Conclusion
In this study, we introduced a fully CMOS-compatible ternary inverter that operates with a memory function using FBFETs. The ternary inverter exhibited three logic states of '− 1' , '0' , and '1' with a high voltage gain of approximately 73 V/V owing to the positive feedback mechanism. Moreover, the ternary inverter retained the logic states during the holding operation, and exhibited a logic holding time and reliable endurance of approximately 150 s and 10 5 , respectively. Hence, the proposed ternary inverter provides possibilities for a new computing paradigm in multivalued logic applications using its memory function.